1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming conductive bump structures on integrated circuit devices and devices comprising such structures.
2. Description of the Related Art
In the manufacture of modern integrated circuits, it is usually necessary to provide electrical connections between the various semiconductor chips making up a microelectronic device. Depending on the type of chip and the overall device design requirements, these electrical connections may be accomplished in a variety of ways, such as, for example, by wire bonding, tape automated bonding (TAB), flip-chip bonding, and the like. In recent years, the use of flip-chip technology, wherein semiconductor chips are attached to substrates, carriers, or other chips by means of solder balls formed from so-called solder bumps, has become an important aspect of the semiconductor processing industry. In flip-chip technology, solders balls are formed on a contact layer of at least one of the chips that is to be connected, such as, for example, on a dielectric passivation layer formed above the last metallization layer of a semiconductor chip comprising a plurality of integrated circuits. Similarly, adequately sized and appropriately located bond pads are formed on another chip, such as, for example, a carrier package, each of which corresponds to a respective solder ball formed on the semiconductor chip. The two units, i.e., the semiconductor chip and carrier package, are then electrically connected by “flipping” the semiconductor chip and bringing the solder balls into physical contact with the bond pads, and performing a “reflow” process so that each solder ball bonds to a corresponding bond pad. Typically, hundreds, or even thousands, of solder bumps may be distributed over the entire chip area, thereby providing, for example, the I/O capability required for modern semiconductor chips that usually include complex circuitry, such as microprocessors, storage circuits, three-dimensional (3D) chips, and the like, and/or a plurality of integrated circuits forming a complete complex circuit system.
FIGS. 1A-1F depict one illustrative prior art process flow for forming conductive bumps for a semiconductor device. FIG. 1A depicts an illustrative prior art device 100 at an early stage of manufacture. As shown therein, a plurality of conductive pads 12 are formed in a layer of insulating material 10. An illustrative passivation layer 14 is formed above the layer of insulating materials. In one illustrative example, the passivation layer 14 may be comprised of multiple layers of material. More specifically, in the depicted example, the passivation layer 14 may be comprised of a layer of silicon-carbon-nitride (BLOK) 14A having an illustrative thickness of about 100 nm, a layer of silicon dioxide 14B having an illustrative thickness of about 450 nm and a layer of silicon nitride having an illustrative thickness of about 400 nm. The layers 14A, 14B and 14C may be formed using traditional deposition processes, such as chemical vapor deposition (CVD) processes.
Next, as shown in FIG. 1B, openings 16 are formed in the passivation layer 14 to thereby expose portions of the conductive pads 12. The openings 16 may be formed using traditional photolithography and etching processes. More specifically, one or more etching processes are performed through a patterned photoresist mask (not shown) to form the openings 16. The size of the openings may vary depending upon the particular application.
Next, as shown in FIG. 1C, a polyimide layer 18 is formed. The polyimide layer 18 is typically formed by initially depositing the polyimide material using a spin-coating technique, and thereafter performing a heating process at a temperature of, for example, about 360° C., to cure the polyimide layer 18. In some case, the polyimide layer 18 may have a thickness of about 2-10 microns. Unfortunately, during the process of forming the polyimide layer 18, oxide material 19, e.g., copper oxide, forms at the interface between the polyimide layer 18 and the conductive pad 12. It should be noted that, although the oxide material 19 is depicted as being a uniform layer, in practice the oxidation may not be so uniformly distributed across the conductive pad 12. The presence of such oxide material 19 may tend to locally increase the resistance between the conductive pad 12 and the conductive bump that will be formed above the conductive pad 12. Such increased resistance may reduce the performance capabilities of the resulting semiconductor device.
FIG. 1D depicts the device 100 after several process operations have been performed. First, the polyimide layer 18 has been patterned using known photolithography and etching techniques. More specifically, one or more etching processes are performed through a patterned photoresist mask (not shown) formed above the polyimide layer 18 to form the patterned polyimide layer 18 depicted in FIG. 1D. Then, an under-bump metallization (UBM) layer 20 is blanket-deposited across the device 100. The UBM layer 20 may be comprised of multiple layers of material and it may be formed by performing one or more deposition processes. In one example, the UBM layer 20 may be comprised of an initial layer of titanium and a second layer of copper.
Then, as shown in FIG. 1E, a patterned mask layer 22, e.g., a photoresist mask, is formed above the device 100 and conductive material 24 for the conductive bump is formed on the device 100. In one illustrative example, a plating process is performed to form a layer of nickel (not shown) on the exposed portions of the device followed by another playing process that forms the bulk of the conductive material 24. In one illustrative example, the conductive material 24 is comprised of tin-silver, but other materials may also be used.
FIG. 1F depicts the device 100 after additional process operations have been performed. Initially, the patterned mask layer 22 (see FIG. 1E) is removed. Thereafter, a heating or reflow process is performed which results in the formation of the illustrative conductive bumps 24B shown in FIG. 1F.
The present disclosure is directed to various methods of forming conductive bumps on a semiconductor device that may at least reduce or eliminate one or more of the problems identified above.